`timescale 1ns/1ps

module  sync_w2r(      
                  //output
                  wp_s,

                 //input           
                  rd_clk,
                  rd_rst,
                  rd_clr,
                  wp_gray
                 );
                 
  parameter aw=10;                 

output [aw:0]  wp_s;    

input          rd_clk;
input          rd_rst;
input          rd_clr;
input  [aw:0]  wp_gray;

reg    [aw:0]  wp_p;  
reg    [aw:0]  wp_s;    

  
////////////////////////////////////////////////////////////////////
//
// Synchronization Logic
//

// write pointer
always @(posedge rd_clk  or negedge rd_rst)
if(!rd_rst)	
begin
	wp_p <= #1 {aw+1{1'b0}};
	wp_s <= #1 {aw+1{1'b0}};	
end
else if(rd_clr)	
begin
	wp_p <= #1 {aw+1{1'b0}};
	wp_s <= #1 {aw+1{1'b0}};	
end	
else
begin
	wp_p <= #1 wp_gray;
	wp_s <= #1 wp_p;	
end	
  	  
	  
endmodule	  
	  